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Energy efficient scheduling for datapath synthesis

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2 Author(s)
Mohanty, S.P. ; Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA ; Ranganathan, N.

In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and resource constrained, utilize the concepts of multiple supply voltage and dynamic clocking for energy minimization. In dynamic clocking, the functional units can be operated at different frequencies depending on the computations occurring within the datapath during a given clock cycle. The strategy is to schedule high energy units, such as the multipliers at lower frequencies such that they can be operated at lower voltages to reduce energy consumption and the low energy units, such as adders at higher frequencies, to compensate for speed. The algorithms have been applied to various high level synthesis benchmark circuits under different time and resource constraints. The experimental results show that for the time constrained algorithm, energy savings in the range of 33-75% are obtained. Similarly, for the resource constrained algorithm, under various resource constraints using two supply voltage levels (5.0 V, 3.3 V), energy savings in the range of 24 - 53% can be obtained.

Published in:

VLSI Design, 2003. Proceedings. 16th International Conference on

Date of Conference:

4-8 Jan. 2003

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