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Power-profile driven variable voltage scaling for heterogeneous distributed real-time embedded systems

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2 Author(s)
Jiong Luo ; Dept. of Electr. Eng., Princeton Univ., NJ, USA ; Jha, N.K.

Presents a power-aware real-time distributed embedded system scheduling algorithm. It tries to satisfy the hard real-time constraints and precedence relationships of the tasks in the distributed embedded system specification. At the same time, it performs variable voltage scaling by addressing variations in power consumption of different tasks and characteristics of different voltage-scalable processing elements (PEs) in an effective and efficient manner. It performs execution order optimization of scheduled events to increase the chances of scaling down voltages and frequencies of these voltage-scalable PEs in the distributed embedded system. It also performs power-profile and timing-constraint driven slack allocation to maximize power reduction via voltage scaling. This scheduling algorithm is also very effective in the case where the variations in power consumption of different tasks can be ignored. It can be included in the inner loop of a system-level synthesis tool for real-time heterogeneous embedded systems since it is very fast. It is superior to other approaches in the literature in terms of power consumption or complexity.

Published in:

VLSI Design, 2003. Proceedings. 16th International Conference on

Date of Conference:

4-8 Jan. 2003