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Static test compaction for full-scan circuits based on combinational test sets and non-scan sequential test sequences

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2 Author(s)
I. Pomeranz ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; S. M. Reddy

We propose a new static compaction procedure for scan circuits that generates a test set with a reduced test application time. The proposed procedure combines the advantages of two earlier static compaction procedures, one that tends to generate large numbers of tests with short primary input sequences, and one that tends to generate small numbers of tests with long primary input sequences. The proposed procedure starts from a test set with a large number of tests and long primary input sequences, and it selects a subset of the tests and subsequences of their primary input sequences. It thus has the flexibility of finding an appropriate balance between the number of tests and the lengths of the primary input sequences in order to minimize the test application time.

Published in:

VLSI Design, 2003. Proceedings. 16th International Conference on

Date of Conference:

4-8 Jan. 2003