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Digital watermarking is a technique of embedding imperceptible information into digital documents. In this paper, a VLSI implementation of the digital watermarking technique is presented for 8 bit gray scale images. This implementation of fragile invisible watermarking is carried out in the spatial domain. The standard ASIC design flow for a 0.13 μm CMOS technology has been used to implement the algorithm. The area of the chip is 3453×3453 μm2 and the power consumption is 37.6 μW.