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Formal verification using bounded model checking: SAT versus sequential ATPG engines

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3 Author(s)
Saab, D.G. ; Dept. of Electr. Eng. & Comput. Sci., Case Western Reserve Univ., Cleveland, OH, USA ; Abraham, J.A. ; Vedula, V.M.

Industry is beginning to use Satisfiability (SAT) solvers extensively for formally verifying the correctness of digital designs. In this paper we compare the performance of SAT solvers with sequential Automatic Test Pattern Generation (ATPG) techniques for property verification. Our experimental results on the ISCAS benchmarks as well as a model of the 8085 microprocessor show that, contrary to popular belief, ATPG techniques perform much better than SAT based verification techniques, especially for large designs.

Published in:

VLSI Design, 2003. Proceedings. 16th International Conference on

Date of Conference:

4-8 Jan. 2003