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Substrate bias effect on cycling induced performance degradation of flash EEPROMs

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3 Author(s)
Mahapatra, S. ; Dept. of Electr. Eng., Indian Inst. of Technol., Bombay, India ; Shukuri, S. ; Bude, J.

Cycling induced performance degradation of flash EEPROMs has been reported for VB=0 and VB<0 programming operation. Compared to VB=0, VB<0 programming shows lower interface degradation for identical cumulative charge fluence (for program) during repetitive program/erase cycling. Reduction in programming gate current has been found to be lower for VB<0 operation under identical interface damage as the VB=0 case. As a consequence, programming under VB<0 condition has been found to cause lower degradation of programming time and programmed VT due to cycling.

Published in:

VLSI Design, 2003. Proceedings. 16th International Conference on

Date of Conference:

4-8 Jan. 2003