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This paper analyzes in detail the fringing induced barrier lowering (FIBL) in MOS transistors with high-k gate dielectrics using 2D device simulations. We found that the device short channel performance is degraded with increase in gate dielectric permittivity (Kgate) due to an increase in the dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate insulator. This fact is validated by extensive device simulations with different channel length and overlap length over a wide range of dielectric permittivities. We also observe that the overlap length is an important parameter for optimizing DC performance in short channel MOS transistors. The effect of stacked gate dielectric and lateral channel engineering on the performance of high-k gate dielectric MOS transistors is also studied to substantiate the above observations.