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Low power technology mapping for LUT based FPGA - a genetic algorithm approach

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2 Author(s)
R. Pandey ; Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., India ; S. Chattopadhyay

In this paper we consider the problem of LookUp Table (LUT) based FPGA technology mapping for power minimization in combinational circuits. The problem has been previously proven to be NP-complete and here we present an efficient Genetic Algorithm solution for it. Considering that the connection switches possess large resistance and capacitance in LUT based FPGA, the fitness of the chromosome is selected based on its ability to reduce the transition probability on "visible" edges of mapped logic circuits by hiding the paths with high transition activity in the "invisible" edges. Meanwhile, the number of LUT is also kept small.

Published in:

VLSI Design, 2003. Proceedings. 16th International Conference on

Date of Conference:

4-8 Jan. 2003