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An efficient multi-level partitioning algorithm for VLSI circuits

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2 Author(s)
Jong-Sheng Cherng ; Dept. of Electr. Eng., Da Yeh Univ., Changhwa, Taiwan ; Sao-Jie Chen

In this paper, a new multi-level bipartitioning algorithm MLP, which integrates a clustering technique and an iterative improvement based partitioning process, is proposed to enhance the stability and the quality of partitioning results. The proposed clustering algorithm is used to reduce the partitioning complexity and improved the performance of partitioning. To generate a high-quality partitioning solution, a module migration based partitioning algorithm MMP is also proposed as the based partitioner for the MLP algorithm. The MMP algorithm implicitly promotes the move of clusters during the module migration processes by paying more attention to the neighbors of moved modules, relaxing the size constraints temporarily during the migration process, and controlling the module migration direction. Experimental results obtained show that the MLP algorithm generates high-quality partitioning results. The MLP algorithm outperforms MELO and CDIPLA3 by 23% and 10%, respectively and is competitive with hMetis and MLc which have generated better results than many recent state-of-the-art partitioning algorithms.

Published in:

VLSI Design, 2003. Proceedings. 16th International Conference on

Date of Conference:

4-8 Jan. 2003