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Timing minimization by statistical timing hMetis-based partitioning

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2 Author(s)
Ababei, C. ; Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA ; Bazargan, K.

In this paper we present statistical timing driven hMetis-based partitioning. We approach timing driven partitioning from a different perspective: we use the statistical timing criticality concept to change the partitioning process itself. We exploit the hyperedge coarsening scheme of the hMetis partitioner for our timing minimization purpose. This allows us to perform partitioning such that the most critical nets in the circuit are not cut and therefore timing minimization can be achieved. The use of the hMetis partitioning algorithm makes our partitioning methodology fast. Simulations results show that 22% average delay improvement can be obtained. Furthermore, as a result of using the statistical timing model, the partitioning results can tolerate changes in temperature and process variation, hence causing less delay change compared to partitioning using static timing models.

Published in:

VLSI Design, 2003. Proceedings. 16th International Conference on

Date of Conference:

4-8 Jan. 2003