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High level modeling and validation methodologies for embedded systems: bridging the productivity gap

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4 Author(s)
S. K. Shukla ; Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA ; S. A. Edwards ; J. P. Talpin ; R. K. Gupta

In this tutorial, we cover the most recent developments in system level design languages and models of computation which influence the choices of modeling paradigms and languages, interoperability of design components created with different modeling styles and languages, synchronous vs. asynchronous system design, and corresponding methodologies based on de-synchronization which leads to new embedded hardware/software co-design methods, formal validation of system level design of embedded hardware/software systems, and component composition frameworks that allows reuse of intellectual properties, and provides efficient simulation and validation environments.

Published in:

VLSI Design, 2003. Proceedings. 16th International Conference on

Date of Conference:

4-8 Jan. 2003