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Reduced in-lock error DLL-based clock synthesiser with novel charge pump phase comparator

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3 Author(s)
Jingcheng Zhuang ; Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada ; Qingjin Du ; Kwasniewski, T.

A reduced in-lock error and low jitter delay-locked loop (DLL)-based clock synthesiser employing a novel phase comparator and charge pump is proposed. HSPICE simulation results show the performance of this DLL-based synthesiser to be significantly better than that of other reported circuits. In particular, it has smaller in-lock error and lower output jitter.

Published in:

Electronics Letters  (Volume:39 ,  Issue: 1 )