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Adaptive Miller capacitor multiplier for compact on-chip PLL filter

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3 Author(s)
Tang, Y. ; Qualcomm Inc., San Diego, CA, USA ; Ismail, M. ; Bibyk, S.

An adaptive Miller capacitor multiplier is proposed to reduce on-chip phase-locked loop (PLL) capacitor area and improve lock speed. Fabricated in 0.5 μm standard CMOS, an effective capacitance of 576 pF is achieved with a polycapacitor of only 192 pF (62% die area saving) and 0.43 mA current consumption. The lock time is reduced by 36% due to the adaptive loop bandwidth control during PLL settling.

Published in:

Electronics Letters  (Volume:39 ,  Issue: 1 )