Referenced Items are not available for this document.
Owing to the sequential nature of memory interfaces, as well as the growing processor-memory performance gap, the design of parallel image processors is often faced with a challenge in deciding memory organisation and distribution. This work addresses the problem of memory access bottlenecks in parallel digital image processors and presents one solution which demonstrates up to 93.4% reduction over standard sequential methods.
Published in:
Electronics Letters
(Volume:39
,
Issue:
1
)
Date of Publication: 9 Jan. 2003
- Page(s):
- 33 - 35
- ISSN :
- 0013-5194
- INSPEC Accession Number:
- 7511844
- Digital Object Identifier :
- 10.1049/el:20030020
- Date of Current Version :
- 28 February 2003
- Issue Date :
- 9 Jan. 2003
- Sponsored by :
- Institution of Engineering and Technology
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