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An evolutionary strategy to design an on-chip test pattern generator without prohibited pattern set (PPS)

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5 Author(s)
Ganguly, N. ; Comput. center, IISWBM, Calcutta, India ; Nandi, A. ; Das, S. ; Sikdar, B.K.
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This paper reports the design of an on-chip Test Pattern Generator (TPG) for VLSI circuits that avoids generation of a given Prohibited Pattern Set (PPS). The design ensures desired pseudo-random quality of the test patterns generated while ensuring fault coverage close to the figures achieved with a typical Pseudo Random Pattern Generator (PRPG) designed around maximal length LFSR/CA. The theoretical framework of CA has provided the foundation of this work. A GA based evolution scheme is employed to achieve the desired TPG developed over the theory of cellular automata.

Published in:

Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian

Date of Conference:

18-20 Nov. 2002