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A genetic testing framework for digital integrated circuits

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4 Author(s)
Xiaoming Yu ; Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA ; Fin, A. ; Fummi, F. ; Rudnick, E.M.

In order to reduce the time-to-market and simplify gate-level test generation for digital integrated circuits, GA-based functional test generation techniques are proposed for behavioral and register transfer level designs. The functional tests generated can be used for design verification, and they can also be reused at lower levels (i.e. register transfer and logic gate levels) for testability analysis and development. Experimental results demonstrate the effectiveness of the method in reducing the overall test generation time and increasing the gate-level fault coverage.

Published in:

Tools with Artificial Intelligence, 2002. (ICTAI 2002). Proceedings. 14th IEEE International Conference on

Date of Conference: