VLSI design and implementation of high-speed RS(204,188) decoder

This paper presents a new VLSI design and implementation of a high-speed three-stage pipelining Reed-Solomon (204,188) decoder based on the modified Euclidean algorithm (MEA). A new multiplier and inversion for GF(2/sup m/) are implemented on the composite field GF(2/sup 2n/) (m = 2n), which offers no more than 75% hardware requirements of the standard Mastrovito multiplier and ROM respectively. By setting the new initial conditions of MEA, a novel parallel MEA architecture is proposed to reuse the registers and multipliers, which can save about 30% hardware overheads compared to the conventional architecture with the same decoding rate. Using 0.25 /spl mu/m CMOS technology, the complexity of the proposed RS decoder is about 30,000 gates with the decoding latency of 239 clock cycles and a throughput of 1.6 Gbit/s.