By Topic

An FPGA-based interface for recording high-speed data stream

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Sun Zhaoyan ; Dept. of Precision Instrum., Tsinghua Univ., Beijing, China ; Dong Yonggui ; Guo Wenxiu ; Xiong Xanping
more authors

An FPGA-based interface for recording high-speed continuous data stream is introduced. The original data stream is input to the interface and reconstructed to four low-speed data streams. Synchronously, by calculating the XOR value of the four corresponding data streams, one checkout code stream is generated. On the other hand, the interface can inversely recover the original data stream while reading. Moreover, when one of the recorded data streams is unreadable, the interface can restore the data stream with the assist of the checkout codes. As the core of this interface, one FPGA chip is selected to implement all the corresponding algorithms. Experimental results show that the interface can work perfectly under the clock of 80 MHz.

Published in:

Communications, Circuits and Systems and West Sino Expositions, IEEE 2002 International Conference on  (Volume:2 )

Date of Conference:

29 June-1 July 2002