An FPGA-based interface for recording high-speed data stream

An FPGA-based interface for recording high-speed continuous data stream is introduced. The original data stream is input to the interface and reconstructed to four low-speed data streams. Synchronously, by calculating the XOR value of the four corresponding data streams, one checkout code stream is generated. On the other hand, the interface can inversely recover the original data stream while reading. Moreover, when one of the recorded data streams is unreadable, the interface can restore the data stream with the assist of the checkout codes. As the core of this interface, one FPGA chip is selected to implement all the corresponding algorithms. Experimental results show that the interface can work perfectly under the clock of 80 MHz.