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Interconnect RC effect has a dominant impact on VLSI performance as the process technology moves towards the sub-micrometer regime. The delays of global interconnects are greater than those of the gates, and the analysis of interconnects becomes indispensable in VLSI design. In this paper, a stable two-pole model is given which matches not only the first two moments as traditional methods do, but adds a zero, in case of unstable conditions being encountered, into the transfer function to improve the stability. The simulation results show that this model can achieve reasonable accuracy.