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The design and measurement results of a CMOS digital 2- and 4-FSK demodulator are presented in this paper. The demodulator is intended for use in direct-conversion high speed radio paging receivers. It is based on a zero-crossing counting and comparing scheme. To improve the bit error rate (BER) performance, a novel technique is utilized, which increases the decision accuracy by generating additional zero-crossings. Simple yet effective clock recovery circuits are included on-chip. The demodulator is fabricated in a 0.35 micron N-well CMOS process and occupies about 0.78 mm2 area. It consumes about 3 mW from a 3-V power supply. Good agreement between measurement and simulation is observed.