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A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops

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3 Author(s)
Wai Chung ; Electr. & Comput. Eng. Dept., Univ. of Waterloo, Ont., Canada ; T. Lo ; M. Sachdev

This paper compares four previously published static dual-edge-triggered flip-flops (DETFFs) with a proposed design for their performance, power dissipation, and low-voltage low-power applications. For each DETFF, the optimal delay, power consumption, and power-delay product are determined as the primary figures of merit. The proposed design is shown to have the least energy at low voltages.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:10 ,  Issue: 6 )