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Instruction-based system-level power evaluation of system-on-a-chip peripheral cores

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3 Author(s)
Givargis, T. ; Dept. of Inf. & Comput. Sci., Univ. of California, Irvine, CA, USA ; Vahid, F. ; Henkel, J.

Various core-based power evaluation approaches for microprocessors, caches, memories and buses have been proposed in the past. We propose a new power evaluation technique that is targeted toward peripheral cores. Our approach is the first to combine for peripherals both gate-level-obtained power data with a system-level simulation model written in an object-oriented language. Our approach decomposes peripheral functionality into so-called instructions. The approach can be applied with three increasingly fast methods: system simulation, trace simulation or trace analysis. We show that our models are sufficiently accurate in order to make power-related system-level design decisions but at a computation time that is orders of magnitude faster than a gate-level simulation.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:10 ,  Issue: 6 )

Date of Publication:

Dec. 2002

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