Cart (Loading....) | Create Account
Close category search window
 

Net-based force-directed macrocell placement for wirelength optimization

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Alupoaei, S. ; Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA ; Katkoori, S.

We propose a net-based hierarchical macrocell placement such that "net placement" dictates the cell placement. The proposed approach has four phases. 1) Net clustering and net-level floorplanning phase: a weighted net dependency graph is built from the input register-transfer-level netlist. Clusters of nets are then formed by clique partitioning and a net-cluster level floorplan is obtained by simulated annealing. The floorplan defines the regions where the nets in each cluster must be routed. 2) Force-directed net placement phase: a force-directed net placement is performed which yields a coarse net-level placement without consideration for the cell placement. 3) Iterative net terminal and cell placement phase: a force-directed net and cell placement is performed iteratively. The terminals of a net are free to move under the influence of forces in the quest for optimal wire length. The cells with high net length cost may "jump" out of local minima by ignoring the rejection forces. The overlaps are reduced by employing electrostatic rejection forces. 4) Overlap removal and input/output (I/O) pin assignment phase: Overlap removal is performed by a grid-based heuristic. I/O pin assignment is performed by minimum-weight bipartite matching. Placements generated by the proposed approach are compared with those generated by Cadence Silicon Ensemble and the O-tree floorplanning algorithm. On average, the proposed approach improves both the total wire length and longest wire length by 18.9% and 28.3%, respectively, with an average penalty of 5.6% area overhead.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:10 ,  Issue: 6 )

Date of Publication:

Dec. 2002

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.