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This paper discusses a new interconnect-aware AMS design methodology which leads to better designs, and is in many ways superior to the RLC post-layout extraction approach. This methodology uses high bandwidth on-chip transmission lines (T-lines) for critical interconnect. The T-lines have been designed for multi-layered metallization stack high speed silicon based technologies, such as the silicon germanium (SiGe) technology, as well as for high speed CMOS technologies.
Date of Conference: 1 Dec. 2002