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Theoretical system-level limits of power dissipation reduction under a performance constraint in VLSI microprocessor design

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1 Author(s)
Olivieri, N. ; Dept. of Electron. Eng., Rome Univ., Italy

This paper provides a quantitative understanding of the relations among supply-voltage scaling, sustainable cycle time, pipeline depth, instruction-level parallelism, and power dissipation. Starting from simple well-established formulas, the analysis show that there is an optimal sizing of the target supply voltage and pipeline stage complexity to minimize power under a performance constraint. The verification of the model on five real processors is reported and discussed, and the application to an ideal microprocessor design or redesign is illustrated.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:10 ,  Issue: 5 )

Date of Publication:

Oct. 2002

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