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A microcoded elliptic curve processor using FPGA technology

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2 Author(s)
P. H. W. Leong ; Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, China ; I. K. H. Leung

The implementation of a microcoded elliptic curve processor using field-programmable gate array technology is described. This processor implements optimal normal basis field operations in F(2/sup n/). The design is synthesized by a parameterized module generator, which can accommodate arbitrary n and also produce field multipliers with different speed/area tradeoffs. The control part of the processor is microcoded, enabling curve operations to be incorporated into the processor and hence reducing the chip's I/O requirements. The microcoded approach also facilitates rapid development and algorithmic optimization: for example, projective and affine coordinates were supported using different microcode. The design was successfully tested on a Xilinx Virtex XCV1000-6 device and could perform an elliptic curve multiplication over the field F(2/sup n/) using affine and projective coordinates for n=113,155, and 173.

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:10 ,  Issue: 5 )