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Multiple-gate SOI MOSFETs: device design guidelines

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2 Author(s)
Jong-Tae Park ; Deptartment of Electron. Eng., Univ. of Incheon, South Korea ; Colinge, J.

This paper describes computer simulations of various SOI MOSFETs with double and triple-gate structures, as well as gate-all-around devices. The concept of a triple-gate device with sidewalls extending into the buried oxide (hereby called a "Π-gate" or "Pi-gate" MOSFET) is introduced. The Pi-gate device is simple to manufacture and offers electrical characteristics similar to the much harder to fabricate gate-all-around MOSFET. To explore the optimum design space for four different gate structures, simulations were performed with four variable device parameters: gate length, channel width, doping concentration, and silicon film thickness. The efficiency of the different gate structures is shown to be dependent of these parameters. The simulation results indicate that the the Pi-gate device is a very promising candidate for future nanometer MOSFET applications.

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Electron Devices, IEEE Transactions on  (Volume:49 ,  Issue: 12 )