By Topic

Heating effects of clock drivers in bulk, SOI, and 3-D CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Liu, C.C. ; Sch. of Electr. & Comput. Eng., Cornell Univ., Ithaca, NY, USA ; Jifeng Zhang ; Datta, A.K. ; Tiwari, S.

Steady-state and transient thermal behavior of the highest power density element in systems and chips-the clock driver-in bulk, silicon-on-insulator (SOI), and three-dimensional (3-D) CMOS is examined. Despite significant metal wiring, a majority of the heat conducts through the buried oxide (BOX) in SOI and the buried interconnect layer in 3-D CMOS. 3-D CMOS has the potential to improve substantially over SOI CMOS in thermal behavior by increasing the wiring density directly beneath the clock driver. Temperature mismatch (important for analog applications) between device planes in 3-D CMOS occurs within a characteristic length, which is as large as 13 μm for clock drivers. These results suggest advantages and architectural options for the design of high-power devices in 3-D integration.

Published in:

Electron Device Letters, IEEE  (Volume:23 ,  Issue: 12 )