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Steady-state and transient thermal behavior of the highest power density element in systems and chips-the clock driver-in bulk, silicon-on-insulator (SOI), and three-dimensional (3-D) CMOS is examined. Despite significant metal wiring, a majority of the heat conducts through the buried oxide (BOX) in SOI and the buried interconnect layer in 3-D CMOS. 3-D CMOS has the potential to improve substantially over SOI CMOS in thermal behavior by increasing the wiring density directly beneath the clock driver. Temperature mismatch (important for analog applications) between device planes in 3-D CMOS occurs within a characteristic length, which is as large as 13 μm for clock drivers. These results suggest advantages and architectural options for the design of high-power devices in 3-D integration.