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Fault tolerance in linear systolic arrays using time redundancy

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3 Author(s)
A. Majumdar ; Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA ; C. S. Raghavendra ; M. A. Breuer

A linear systolic array with fault-tolerant capabilities is developed. Fault tolerance is based on triple time redundancy, and the requisite modifications of the interconnection, switching and control structures to achieve this are discussed. The array is capable of reconfiguring itself in a distributed manner, leading to graceful degradation. Because of the degradations, the algorithms executing on the array need to be remapped. A method for restructuring algorithms and executing them on a degraded array is presented. The reliability analysis of the system is carried out and is compared with the reliability of nonredundant systolic arrays. The reliability analysis of a system with only the capability of single error correction is also presented. The performability of the system, with running time and throughput as performance metrics, is estimated.<>

Published in:

System Sciences, 1988. Vol.I. Architecture Track, Proceedings of the Twenty-First Annual Hawaii International Conference on  (Volume:1 )

Date of Conference:

0-0 1988