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A systematic methodology for the reduction of the power consumption and the execution time in realizations of multimedia applications on programmable processors is proposed. The methodology is mainly based on the application of data transfer and storage optimizing code transformations to a high-level description of the target algorithm. Application of the code transformations according to the proposed order moves the main part of the memory accesses from the large background memories (lying possibly off-chip) to smaller ones (on-chip) or even to foreground storage. Data cache performance is improved as well. In this way the power consumption in the data memory hierarchy of the target processor and in the related interconnect, which forms a significant part of the total power budget of the system, is significantly reduced. Execution time and the power consumption due to instruction storage and transfers are reduced as well after the application of the proposed methodology. Experimental results from real-life applications prove the effectiveness of the proposed methodology.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:10 , Issue: 4 )
Date of Publication: Aug. 2002