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System-level exploration for Pareto-optimal configurations in parameterized system-on-a-chip

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3 Author(s)
Givargis, T. ; Dept. of Inf. & Comput. Sci., Univ. of California, Irvine, CA, USA ; Vahid, F. ; Henkel, J.

In this work, we provide a technique for efficiently exploring the power/performance design space of a parameterized system-on-chip (SOC) architecture to find all Pareto-optimal configurations. These Pareto-optimal configurations will represent the range of power and performance tradeoffs that are obtainable by adjusting parameter values for a fixed application that is mapped on the SOC architecture. Our approach extensively prunes the potentially large configuration space by taking advantage of parameter dependencies. We have successfully applied our technique to explore Pareto-optimal configurations of our SOC architecture for a number of applications.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:10 ,  Issue: 4 )