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A network flow approach to memory bandwidth utilization in embedded DSP core processors

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1 Author(s)
C. H. Gebotys ; Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Canada

This paper presents a network flow approach to solving the register binding and allocation problem for multiword memory access DSP processors. In recently announced DSP processors, 16-bit instructions which simultaneously access four words from memory are supported. A polynomial-time network flow methodology is used to allocate multiword accesses, including constant data-memory layout, while minimizing code size. Results show that improvements of up to 87% in terms of memory bandwidth are obtained compared to compiler-generated DSP code. This research is important for industry since this value-added technique can improve code size and utilize higher-memory bandwidths without increasing cost.

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:10 ,  Issue: 4 )