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Scaling of flash NVRAM to 10's of nm by decoupling of storage from read/sense using back-floating gates

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2 Author(s)
A. Kumar ; Sch. of Electr. & Comput. Eng., Cornell Univ., Ithaca, NY, USA ; S. Tiwari

Conventional floating-gate flash memory structures have limited scalability due to nonscaling of insulators for charge retention and reliability, inefficiency of hot-electron injection processes at nanometer dimensions due to off-equilibrium overshoot effects, poor short-channels effects due to poor electrostatics and large voltages needed at the control/read gate as a result of voltage leveraging. We present and analyze a new nonvolatile memory structure based on back-floating gate, which decouples the read/sensing from storage/programming and thus allows a design with efficient storage and improved injection and short-channel characteristics. This structure can be scaled to dimensions similar to that of high performance transistors, i.e., 10's of nanometers, without compromising the requirements of insulator thickness. Characteristics of the structure are analyzed using coupled simulation and modeling that employs Monte Carlo simulation for hot carrier analysis and quasistatic calculation for evaluating charge injection and storage. We compare the characteristics of the new structure with conventional structures and their use as a memory cell.

Published in:

IEEE Transactions on Nanotechnology  (Volume:1 ,  Issue: 4 )