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High-performance strained Si/SiGe pMOS devices with multiple quantum wells

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5 Author(s)
N. Collaert ; Interuniversity Micro-Electron. Center, Heverlee, Belgium ; P. Verheyen ; K. De Meyer ; R. Loo
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This paper describes the fabrication and results of the electrical characterization of buried channel Si/SiGe pMOS devices using double and single quantum wells. The devices have been fabricated in an almost standard CMOS technology including shallow trench isolation, rapid thermal annealing, and standard Co/Ti silicidation. The incorporation of 15% and 32% channels provides a strong enhancement (up to 85%) in long-channel mobility. This increased mobility behavior is translated into a 55% higher on-state current for the long-channel devices and a 13% higher on-state current (Vgs-VT= -1 V and Vds= -1.5 V) for devices down to Lmask=70 nm while maintaining low leakage and good short-channel and drain induced barrier lowering behavior.

Published in:

IEEE Transactions on Nanotechnology  (Volume:1 ,  Issue: 4 )