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Design considerations using parasitic-aware synthesis and optimisation techniques are presented for a three-stage 30 dBm 900 MHz class-E power amplifier implemented in a 0.35 μm standard digital CMOS process. Using both bond wire and on-chip square spiral inductors, the PA achieves 49% drain efficiency η and 25 dB power gain using a single 3.3 V power supply. Experience shows that the class-E PA design space is complex with many local minima. Thus, simulated annealing optimisation is chosen because of its inherent hill climbing ability that allows it to avoid being trapped in sub-optimum local minima. The paper first demonstrates the severe effects or parasitics by comparing results of switching power amplifier designs with both parasitic-free and parasitic-laden on-chip inductors. The results of parasitic-aware synthesis are then presented, including an illustration of its potential for power amplifier topology selection.