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2 GHz controllable power amplifier in standard CMOS process for short-range wireless applications

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2 Author(s)
M. M. Hella ; Analog VLSI Lab., Ohio State Univ., Columbus, OH, USA ; M. Ismail

The authors present the design and implementation of a broadband radiofrequency power amplifier in a standard CMOS technology for short-range wireless applications. The amplifier is implemented in a standard 0.35 μm triple metal CMOS process. The amplifier is capable of delivering a maximum output power of 16.6 dBm at 1.91 GHz, and of 16 dBm at 2 GHz using a 3.3 V supply with an overall measured power added efficiency (PAE) of 33%. The power amplifier employs a class AB output stage, which represents a compromise between efficiency and linearity. The level of output power can be controlled in 2 dB steps using a number of parallel semi-cascode stages.

Published in:

IEE Proceedings - Circuits, Devices and Systems  (Volume:149 ,  Issue: 56 )