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Efficient path-delay fault simulation for standard scan design

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1 Author(s)
Kang, S. ; Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea

In spite of using scan designs, there remain problems concerning the generation and confirmation or test vectors for potential timing problems. Most fault simulators for path-delay faults rely on the use of augmented scan flip-flops to convert the timing vector problem to a purely combinational one. The paper describes an efficient path-delay fault simulation algorithm for standard scan environments. The new simulation algorithm using various new logic values is based on the parallel-pattern-single-fault-propagation technique. The experimental results show the efficiency of the new algorithm.

Published in:

Circuits, Devices and Systems, IEE Proceedings -  (Volume:149 ,  Issue: 56 )

Date of Publication:

Oct/Dec 2002

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