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Stress analysis is of crucial importance in the design of components and systems in the electronics industry. In this paper, the authors present a new strength criterion combined with finite element analysis (FEA) to predict the failure stress of silicon die. Several different models of pushers were designed to apply load in the vfBGA reliability test until some units failed the electrical test. Meanwhile, finite element analysis was performed in order to find the location of the highest stress and the expected modes of failure. In the simulation, a parametric study of the effect of different types of pushers on the internal stress of the die is carried out and the failure stress can be determined eventually. The potential for chip damage under certain pushers during electrical tests has been assessed and the relationship between the maximum principal stress and the thickness of the silicon die is also explored.