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A capacitorless double-gate DRAM cell design for high density applications

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3 Author(s)
Kuo, C. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Tsu-Jae King ; Chenming Hu

Experimental measurements and 2-D device simulation are used to investigate a capacitorless, asymmetric double-gate DRAM (DG-DRAM) design. Soft error problems are discussed. Careful attention to cell geometry and film quality results in intrinsic retention times suitable for stand-alone and embedded memories.

Published in:

Electron Devices Meeting, 2002. IEDM '02. International

Date of Conference:

8-11 Dec. 2002