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Device performance of sub-50 nm CMOS with ultra-thin plasma nitrided gate dielectrics

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19 Author(s)
Inaba, S. ; SoC Res. & Dev. Center, Toshiba Corp. Semicond. Co., Yokohama, Japan ; Shimizu, T. ; Mori, S. ; Sekine, K.
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In this paper, the physical and electrical characteristics of ultra-thin plasma nitrided gate dielectrics are reported, aiming for sub-50 nm gate length CMOS applications. The impact of plasma nitridation conditions on DC characteristics was investigated extensively by changing nitrogen plasma pressure, plasma immersion time, or plasma generation power. NBTI has been also investigated and the lifetime at 105/spl deg/C and 0.85 V operation is estimated to be about 10 years. The final current drives of 690 /spl mu/A//spl mu/m for nFET and 301 /spl mu/A//spl mu/m for pFET at Vdd = 0.85 V (Ioff = 100 nA//spl mu/m) have been achieved in sub-50 nm CMOS with optimized plasma nitrided gate dielectric with EOT <1.2 nm.

Published in:

Electron Devices Meeting, 2002. IEDM '02. International

Date of Conference:

8-11 Dec. 2002

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