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14 nm gate length CMOSFETs utilizing low thermal budget process with poly-SiGe and Ni salicide

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20 Author(s)
Hokazono, A. ; SoC Res. & Dev. Center, Toshiba Corp. Semicond. Co., Yokohama, Japan ; Ohuchi, K. ; Takayanagi, M. ; Watanabe, Y.
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High performance 14 nm gate length CMOSFETs are demonstrated in this paper. To acquire a shallow source/drain (S/D) extension profile, the optimization of a low thermal budget process utilizing poly-SiGe and Ni salicide is performed. A poly-SiGe gate electrode minimizes the gate depletion effect, so that a high level of dopant activation in the gate electrode is realized even by low temperature spike annealing. Moreover, short channel characteristics are optimized by using an offset spacer beside the gate electrode. The highest drive current is achieved in 14 nm gate length CMOSFETs reported to date.

Published in:

Electron Devices Meeting, 2002. IEDM '02. International

Date of Conference:

8-11 Dec. 2002