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We have developed 4 Mb 1T1C FeRAM device technology using 0.25 /spl mu/m design rules, which is fully compatible with CMOS logic. This consists of three key technologies: a diffusion barrier and an oxidation barrier to W-plug, low thermal budget process for SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT)-capacitors and no via contact cell scheme.
Electron Devices Meeting, 2002. IEDM '02. International
Date of Conference: 8-11 Dec. 2002