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A novel stack capacitor cell for high density FeRAM compatible with CMOS logic

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18 Author(s)
Hayashi, T. ; Syst. LSI Res. Div., Oki Electr. Ind. Co. Ltd., Tokyo, Japan ; Igarashi, Y. ; Inomata, D. ; Ichimori, T.
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We have developed 4 Mb 1T1C FeRAM device technology using 0.25 /spl mu/m design rules, which is fully compatible with CMOS logic. This consists of three key technologies: a diffusion barrier and an oxidation barrier to W-plug, low thermal budget process for SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT)-capacitors and no via contact cell scheme.

Published in:
Electron Devices Meeting, 2002. IEDM '02. International

Date of Conference: 8-11 Dec. 2002

Page(s):
543 - 546
Print ISBN:
0-7803-7462-2
INSPEC Accession Number:
7509345
Conference Location :
San Francisco, CA, USA
Digital Object Identifier :
10.1109/IEDM.2002.1175899
Product Type:
Conference Publications

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