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A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 /spl mu/m/sup 2/ SRAM cell

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44 Author(s)
Thompson, S. ; Intel Corp., Hillsboro, OR, USA ; Anand, N. ; Armstrong, M. ; Auth, C.
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A leading edge 90 nm technology with 1.2 nm physical gate oxide, 50 nm gate length, strained silicon, NiSi, 7 layers of Cu interconnects, and low k carbon-doped oxide (CDO) for high performance dense logic is presented. Strained silicon is used to increase saturated NMOS and PMOS drive currents by 10-20% and mobility by >50%. Aggressive design rules and unlanded contacts offer a 1.0 /spl mu/m/sup 2/ 6-T SRAM cell using 193 nm lithography.

Published in:

Electron Devices Meeting, 2002. IEDM '02. International

Date of Conference:

8-11 Dec. 2002

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