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Design for scaled thin film strained-SOI CMOS devices with higher carrier mobility

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6 Author(s)
Mizuno, T. ; MIRAI Project, Assoc. of Super-Adv. Electron. Technol., Kawasaki, Japan ; Sugiyama, N. ; Tezuka, T. ; Numata, T.
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Physical mechanisms responsible for the reduction in both electron and hole mobility in thin strained-Si structures of strained-SOI CMOS devices are examined in detail. The slight decrease in electron mobility with thinning strained-Si layers is attributable to the quantum-mechanical confinement effect in strained-Si layers. Also, diffusion of Ge atoms into SiO/sub 2//strained Si interface is found to cause the generation of interface states near valence band edge, leading to the reduction in hole mobility in lower E/sub eff/ region through Coulomb scattering. Based on considerations of these factors affecting mobility, the strained-Si thickness and the Ge content are designed to realize high-speed strained-SOI CMOS under the 65 nm technology and beyond.

Published in:

Electron Devices Meeting, 2002. IEDM '02. International

Date of Conference:

8-11 Dec. 2002