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An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time

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2 Author(s)
Watanabe, T. ; R&D Dept., DENSO CORP, Aichi, Japan ; Yamauchi, S.

An all-digital phase-locked loop (PLL) circuit in which resolution in the phase detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The pulse delay circuit is connected in a ring shape with 32 inverters (25 inverters). With the inverter gate-delay time as the time base, the pulse phase difference is detected simultaneously with the generation of the output clock. In this system, the phase detector and oscillator share a single ring-delay-line (RDL). This means the resolution is the same at all times, making a high-speed response possible. In a prototype integrated circuit (IC) using 0.65-μm CMOS, the generation of a frequency multiplication clock was achieved with four reference clocks, and that of a phase-locked clock with seven reference clocks, for a high-speed response. The cell size was 1.08 × 1.08 mm2, and the output clock frequency had a wide range of 50 kHz∼60 MHz. The multiplication range of the clock frequency was also a very wide 4∼1022, and a high level of precision was achieved with a clock jitter standard deviation of 234 ps. This digital PLL can withstand a broad range of operating environments, from -30°C∼140°C, and is suitable for making a programmable clock generator on a chip.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:38 ,  Issue: 2 )

Date of Publication:

Feb 2003

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