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A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator

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4 Author(s)
H. Nosaka ; NTT Photonics Labs., NTT Corp., Kanagawa, Japan ; K. Ishii ; T. Enoki ; T. Shibata

A clock and data recovery (CDR) circuit with a novel two-mode phase comparator is proposed. The 10-Gb/s CDR integrated circuit (IC) operates both for consecutive identical digits (CID) and data transition density variations. This advance is achieved through the use of our novel two-mode phase comparator, which enables us to determine an optimal phase-locked loop parameter for various data patterns. Experimental results show that the jitter generation of the CDR IC is less than 7 pspp for a 27-1 pseudorandom bit sequence with up to 1024 CIDs. The results also show that the jitter transfer and jitter tolerance are unaffected by data transition density factors of between 1/8 and 1/2.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:38 ,  Issue: 2 )