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Two gates are better than one [double-gate MOSFET process]

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25 Author(s)
P. M. Solomon ; IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA ; K. W. Guarini ; Y. Zhang ; K. Chan
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A planar self-aligned double-gate MOSFET process has been implemented where a unique sidewall source/drain structure (S/D) permits self-aligned patterning of the back-gate layer after the S/D structure is in place. This allows coupling the silicon thickness control inherent in a planar, unpatterned layer with VLSI self-alignment techniques and also gives independently controlled front and back gates. The demanding structure led to process innovations primarily in front-end CMP, where planarity within 5 nm was achieved on an 8-in diameter wafer as well as in silicided silicon source/drain sidewalls, with minimal encroachment of the silicide. Double-gate FET (DGFET) operation is demonstrated, with good transport at both interfaces. Dense circuit layouts are achieved with multifinger devices, and logic inverters with back-gate-controlled load current as well as NOR logic using the two gates of a single transistor as inputs are demonstrated.

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IEEE Circuits and Devices Magazine  (Volume:19 ,  Issue: 1 )