By Topic

CMOS standard cells characterization for IDDQ testing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Pleskacz, W.A. ; Inst. of Microelectron. & Optoelectronics, Warsaw Univ. of Technol., Warszawa, Poland ; Borejko, T. ; Kuzmicz, W.

This paper describes the CMOS standard cells characterization methodology for IDDQ testing. Defect statistics were taken into account and critical area approach was used to generate compact test sets. The proposed methodology allows one to find the types of faults which may occur in a real IC, to determine their probabilities, and to find the input test vectors which detect these faults. Experimental results for gates from an industrial standard cell library were presented. The complete bridging fault set and different types of the simulation conditions of shorts at inputs of logic gates ("Wired-AND" and "Wired-OR" conditions) were considered.

Published in:

Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. 17th IEEE International Symposium on

Date of Conference: