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Fault-tolerant CAM architectures: a design framework

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3 Author(s)
F. Salice ; DEI, Politecnico di Milano, Italy ; M. G. Sami ; R. Stefanelli

Presents a novel design framework for designing fault tolerant/self-checking content addressable memories (CAM). The proposed methodology produces a CAM structural architecture starting from a functional description of some high level properties of the device (design directives). The analysis focuses on the functional level; in particular, the paper concentrates on functional level synthesis, by considering the transformation from the functional description to the structural definition. Some examples will be provided as support to the description.

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Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. 17th IEEE International Symposium on

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