Referenced Items are not available for this document.
Coarse-grained reconfigurable architectures can enhance the performance of critical loops and computation-intensive functions. Such architectures need efficient compilation techniques to map algorithms onto customized architectural configurations. A new compilation approach uses a generic reconfigurable architecture to tackle the memory bottleneck that typically limits the performance of many applications.
Published in:
Design & Test of Computers, IEEE
(Volume:20
,
Issue:
1
)
Date of Publication: Jan-Feb 2003
- Page(s):
- 26 - 33
- ISSN :
- 0740-7475
- INSPEC Accession Number:
- 7519143
- Digital Object Identifier :
- 10.1109/MDT.2003.1173050
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 29 January 2003
- Issue Date :
- Jan-Feb 2003
- Sponsored by :
- IEEE Council on Electronic Design and Automation
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